All About Intel’s 10nm Process Lead

All About Intel’s 10nm Process Lead

Intel gets very hot to fail to get results to the point where they can send 10 nm in volume. We have talked with analysts about how Intel is now behind TSC / Global foundries / Samsung, because in the second half of 2018 plans to roll out 7 nm nodes, while "Intel will still be at 10 nm until 2019". The problem with all this, the idea that the commercial nomenclature of these processes means anything - spoilers: not so.
All About Intel’s 10nm Process Lead
Intel’s 10nm Process Lead

Not all nomenclature is the same, Intel is still under such leadership

Barclays recently downgraded NASDAQ: INTC  cited problems with results of up to 49.7 0.01% of shares and the company lost its process leadership. Analysts cite the fact that Intel started the 10nm process in the second half of 2019, while AMD will already be at 7 nm by the end of the year. He further said that Intel was confident that the company could maintain performance excellence, but there was no evidence provided to display it. I believe that these two claims have many problems and factual errors. So without going further, let's go into a lower character.

The first mistake that most mainstream media is doing right now is comparing processes on a naming basis. For example, compared to 10 nm Intel compared to 10 nm on Samsung or TSMC 7 nm considering Intel 10 nm in the future. The reason is simple, companies can give this procedure the name they want. They can also name 22 nm BEOL processes 22, 14, 12 or 7. Actually, there is no standardization, so to get a good idea you need to look under the hood that is comparable to the node and which is not.

On average, the Intel 10 Nm process is equal to 7 nm types of pure-rotary casting. This example is much comparable to the 12 nm TSMC (which is basically an advanced version of only 16 FF) or Samsung 10 nm process. The correct way to see it is to see how small the transistor is. The Polly Pitch and Metal Layer 2 contacts are usually the best indicators on the scale and millions of transistors per mm2, which gives us real process density.

Now it's funny here, the 10 nm Intel process is actually denser than all 10 nm Pureplay Foundries because it is standing now. Of course, unless we have a volume chip, there is definitely no way to find out, but we have the best guesses (keep in mind that they have been adjusted by Intel for unrealistic claims). At a density of MTX / MM2 106.1, the Intel process is 10 nm better than TSMC, Global Foundries, and the Samsung 7 nm process. Just because it's called 10 nm (it can be called the one-eyed Peter Fabolous process for all naming cases) and in other foundations there will soon be something called 7 Nm, which doesn't mean that Intel is actually behind

Following are the main acquisitions:

  • Intel will compete with 7 nm from the 10-nm pure foundry plant.
  • Intel 10 nm has not reached volume and is expected to do this in 2H 2019.
  • 7 nm (high performance) TSMMC has not come out and 12 nm is not the same as 10 nm Intel.
  • Samsung 7 Nm (high performance) has not come out and the 10 nm process is not the same as Intel 10 nm.
  • The Global Foundries 7 nm have not come out and the 10 nm process is not the same as 10 nm Intel.

So what is the reason for the first delay and what Intel plans to do?

He said, all suggestions are generally looking ahead, so Intel is still in the lead, even if TSMC really reduces the 7 nm process in time, the company will lose this advantage - at least temporarily. By form Before continuing, let's try to find out why the problem occurred in the first place. Our source told us that this was mainly done with Intel who worked too fast. SAQP or Self Aligning Quad Patterning is a technology used by companies to make a 10 nm process and to do this is the first in the industry to do it.

The only problem is that it seems that she had unexpected problems and it was probably a mistake to change it. Intel will take so long to increase the volume that the only reason is that if they were completely redesigning the process. In other words, the processor 10nm he saw in the market for Intel is a different process that would have actually been implemented in 2H 2019, for a new format might mean many things, but we heard rumors that the company step down Is planning to do a level of metal where SAQP will not be required (if you prefer, then a type of Intel 12 nm process). If so, then we will see that the company loses its valuable advantage (but it is not far behind) and there is a process technology that is equal to the rest.

Of course, all of them believe that there is not a problem similar to Intel in the PurePlace Foundry such as TSC, Global Foundries, and Samsung because they will also use SAQP. There is a big difference between your vision and Intel. This is where things become even more complicated, in case of yield, TSMC should have 7 nm and 7 nm + different process. The first will be built using UV (and prone to facing Intel similar problem) while the second will use the UVV, which requires more time to implement but generally should have more results.

So why can not Intel do this and why use the UV? Well, they will. Intel has already invested in Fab 42 in Arizona and it is almost certain that they will use the UV scanner there. Since performance problems are not infectious in generations of processes, we can expect Intel's 7 nm to be originally on track for the scheduled date. Remember, using SAQP was one of the problems, so switching to EUV (which means you need quadruple pattern now to achieve 10nm specifications) to move forward with company 7 nm well Permission should

The main findings are:

  • Due to the use of SAQP using standard lithography, Intel ran into 10 nm problems.
  • The use of the UV could stop him.
  • Intel will be based on NM Fab 42 and will not be affected by the 10 nm delay.
  • TSMC is also using SAQP for the original 7 nm process.
  • Suppose you have problems that ran Intel and thrown in time, we hope that Intel is temporarily equivalent to net play casting before they enter Operation 7 nm and to avoid gaining their profits. Are capable.
  • The actual delay indicator is to see the 7 nm roadmap.

Decision: What we have tried to establish in this article is that it is too early to deploy the process of the death of Intel until TSMC is deployed its NM 7 nm without delay and 2) We confirm that Your node's EUV is getting 7 nm too late. Without these two scenarios, we are seeing a temporary loss of lead which runs for approximately one year after being activated by 7 nm and gets profit or does not make any changes at all.

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